1. Field of the Invention
The invention relates to an integrated circuit from which an error datum is to be read out in accordance with a test mode. The invention also relates to a test system in which a plurality of integrated circuits are to be tested in parallel and error data are to be read out from the integrated circuits. The invention also relates to a method for reading out error data from integrated circuits.
2. Description of the Related Art
Integrated circuits are frequently tested in parallel by connecting the integrated circuits to a tester unit for a test system. In the case of a burn-in operation, in particular, the integrated circuits are simultaneously tested under extreme operating conditions in order to pre-age them.
As a result of the fact that it is necessary to test the integrated circuits simultaneously, a large number of parallel-routed tester channels are needed to connect the address connections, command connections and, in particular, the data connections of the integrated circuits to the tester unit. Particularly in the case of a very large number of integrated circuits which are to be simultaneously tested, it is therefore necessary to use these tester channels as economically as possible. Reducing the number of tester channels also makes it possible to increase the number of integrated circuits which can be simultaneously tested.
The integrated circuits are usually organized in groups and banks and are simultaneously driven in parallel in order to keep the outlay for driving the modules using the tester unit low. All of the integrated circuits are thus essentially driven using common address and command lines. Since the data line, to which the integrated circuits of a group are connected, are likewise connected to the tester unit via a common data bus, special control signals are provided in order to successively read out the data, which need to be read out from the integrated circuits of the group, to the tester unit via the data bus. This is effected in a manner such that only one bank of data can be sent at a time to the tester unit.
The control signal is generally a circuit select signal (e.g., CS: chip select signal) which is provided for the purpose of activating and deactivating the respective integrated circuit. In order to provide this circuit select signal, tester channels are provided between each of the integrated circuits of the group and the tester unit. A respective integrated circuit of a plurality of groups is arranged to form banks, the integrated circuits of a bank each being activated and deactivated using a circuit select signal.
Since, in the case of the burn-in operation of encapsulated integrated circuits, the costs of the receptacles increase with the number of contacts required for testing, on account of the increased contact-making complexity, reducing the number of control lines is associated with a cost advantage.
Particularly in the case of the wafer-level burn-in operation in which the integrated circuits are tested on an unsawn wafer, it is necessary to reduce the number of connections between the tester unit and the wafer to an absolute minimum since such a test system requires a full-wafer contact-making device for the purpose of making contact with the integrated circuits. Such a full-wafer contact-making device is complex since it makes it possible to connect all of the integrated circuits of a wafer to the tester unit and thus may have many times 10,000 connections. The full-wafer contact-making apparatus is also susceptible to errors since the contact-making needles which are used to make contact with the individual contacts of the integrated circuits are very small and are thus sensitive to mechanical influences. The susceptibility to errors thus increases with the number of contact-making needles in the full-wafer contact-making apparatus, with the result that reducing the number of contact-making needles used reduces the susceptibility to errors and thus likewise saves costs.